The present invention generally relates to magnetic storage devices, and, more particularly, to a magnetic storage device equipped with a write driver circuit that enables recording on a magnetic recording medium at a high transfer rate.
In recent years, there has been an increasing demand for higher transfer rates in magnetic storage devices such as hard disk devices and data back-up magnetic tape devices, as a larger amount of information is expected to be processed at once. In response to such a demand, various methods and techniques have been suggested to further improve the recording/reproducing circuits and the magnetic recording media employed in the magnetic storage devices.
In a magnetic storage device such as a hard disk device, a write driver circuit of a head amplifier IC in a read/write circuit applies a high-speed alternating current to a recording head to induce a recording magnetic field. By doing so, the recording head magnetizes a rotating magnetic disk, and records data on the magnetic disk.
FIG. 1 illustrates the structure of a conventional write driver circuit. As shown in FIG. 1, a write driver circuit 100 forms an “H-bridge” circuit including four transistors Q101 through Q104 and a magnetic head 101. In this structure, two transistors diagonally facing each other are switched on to apply current to the magnetic head 101. For instance, the transistors Q101 and Q104 are switched on while the transistors Q102 and Q103 are switched off, so that recording current flows into the magnetic head 101 from a connection point N toward another connection point P. With the recording current, the magnetic head 101 induces an alternating recording magnetic field, and magnetizes a magnetic recording medium (not shown) provided in the vicinity of the magnetic head 101. By doing so, the magnetic head 101 records information on the magnetic recording medium.
However, as the transfer rate increases, it becomes more essential to achieve accurate impedance matching. Therefore, write driver circuits with improved impedance matching processes have been developed in recent years.
FIG. 2 illustrates the structure of one of those write driver circuits. As shown in FIG. 2, a write driver circuit 110 includes a “double H-bridge” circuit including four outer transistors Q111 through Q114, four inner current sources Q111 through CS114, a magnetic head 101, and resistors R101 and R102 that are connected to either end of the magnetic head 101 and perform impedance matching.
The four outer transistors Q111 through Q114 operate in the same manner as the “H-bridge” circuit shown in FIG. 1. More specifically, as shown in FIGS. 3A and 3B, when a recording data signal is inputted to the bases of the transistors Q111 through Q114, the transistors Q111 and Q114 are switched on, and the transistors Q112 and Q113 are switched off. The recording current starts flowing from a connection point P toward another connection point N shown in FIG. 2. When the transistors Q111 and Q114 are switched off and the transistors Q112 and Q113 are switched on, the recording current flows from the connection point N to the connection point P. As a result, recording current having such a waveform as shown in FIG. 3E flows into the magnetic head 101. What is remarkable here is that the waveform of a rise of the recording current is not rectangular but is of the shape of a logarithmic function. This is due to the parasitic inductance in the transmission paths from the transistors to the magnetic head 101 and the inductance of the coil of the magnetic head 101. Here, the waveform is expressed as τ=L/R, with the total sum of the parasitic inductance in the transmission paths and the inductance of the coil of the magnetic head 101 being L, the resistance value of the resistors R101 and R102 being R, and the rise time constant being τ.
The recording current having the above waveform may degrade the overwrite characteristics and the NLTS (Non-Linear Transition Shift) characteristics in recording and reproduction operations. To avoid the degradation, the four current sources CS111 through CS114 apply pulse-type current to the magnetic head 101, so that the magnetism of the magnetic recording medium can be adequately reversed at the rise of the recording current. For example, when transistors Q111 and Q114 shown in FIG. 3A are switched on, the current sources CS111 and CS114 are also switched on for a short period of time, as shown in FIG. 3C. By doing so, pulse-type current flows into the magnetic head 101. Likewise, when the transistors Q112 and Q113 shown in FIG. 3B are switched on, the current sources CS112 and CS113 are switched on for a short period of time, as shown in FIG. 3D. By doing so, recording current having a waveform with an overshooting rise flows into the magnetic head 101, and the media characteristics such as the overwrite characteristics can be improved. However, in this structure, the four current sources CS111 and CS114 are necessary as well as the four transistors Q111 and Q114. As a result, the circuit size becomes larger, and so does the chip size of the head amplifier IC. With the increases in size, a larger amount of heat is generated. Because of this, the head amplifier IC cannot be placed in the vicinity of the magnetic head 101.
As shown in FIG. 2, the write driver circuit 110 also includes the resistors R101 and R102 to match the output impedance of the emitter followers of the transistors Q111 and Q113 with the impedance of the magnetic head 101. For instance, when the transistors Q111 and Q114 are on, the recording current flows from the transistor Q111 to a corrector of the transistor Q114 via the resistor R101, the magnetic head 101, and the resistor R102. However, the input impedance of the corrector of the transistor Q114 is too high, and a reflection wave is generated due to unmatched impedances. As a result, the waveform of the recording current is deformed. To avoid such an undesirable situation, the transistor Q113 is switched on, and current that is 10% or less than the recording current is applied. With the small amount of current flowing into a current source CS115, the input impedance of the corrector of the transistor Q114 is lowered, so that the impedance matching can be performed with the resistors R101 and R102, and a reflection wave can be prevented. In this case, however, there is an increase in power consumption, compared with a case in which the transistor Q113 is not switched on.